Atomic Layer Deposition of Sidewall Spacers: Process, Equipment and Integration Challenges in State-of-the-Art Logic Technologies

Dielectric thin film spacers play a very important role in defining the silicon channel boundary and junction geometries as well as proximity to silicon stressors and strongly affect key transistor electrical characteristics [1]. Another important application of sidewall spacers is in patterning of 3D FinFETs (Field Effect Transistor), where the Sidewall Image Transfer (SIT) technology [2] helps to overcome the limitations of conventional lithography and to improve control of critical dimensions. Sidewall spacers are also used to control critical dimension (CD) by depositing a spacer film inside a feature to achieve a CD shrink. Tolerance for variability of T_Fin(Fin width) has to be in the sub nm range to significantly reduce variability in FinFET performance. The need for precise scaling of conventional spacers as well as new patterning applications put very stringent requirements on spacer thin film depositions and on control of spacer film properties during subsequent integration processes. The need for greatly improved spacer process step coverage, tighter thickness control, pattern effects and more stringent film properties requirements strongly influenced the transition from Chemical Vapor Deposition (CVD) to Atomic Layer Deposition (ALD) spacers in the industry.

This paper discusses the properties of ALD silicon nitride and silicon oxide spacer films from the perspectives of ALD and MLD (Molecular Layer Deposition) techniques, precursor chemistries and compositional stability after subsequent integration steps like implant anneals and spacer sculpting reactive ion etching processes. Advanced imaging techniques like EELS (Electron Energy Loss Spectroscopy) and XPS (X-ray Photoelectron Spectroscopy) techniques have been used to analyze sidewall spacer transformation. Special attention has been paid to the microloading effect - the dependence of thin film deposition rate on pattern density [3]. Microloading data for CVD, MLD and ALD techniques are compared based on a specially designed microloading measurement vehicle. This is especially useful with geometries needing a sub nm tolerance and when patterning endpoint detection schemes are highly dependent on film properties.

The effect of ALD deposition parameters on film electrical characteristics like dielectric breakdown and leakage are also delineated.  Silicon strain engineering issues related to the implementation of ALD spacers and techniques aimed at varying and controlling an intrinsic stress level in ALD films are also discussed. The findings helped to optimize the existing ALD/MLD processes for conventional epi and source/drain spacers as well for oxide sidewall ALD spacers for SIT fins patterning and CD shrink on 14nm FinFET technology.

References:

1. J-H Yan, J-E Park, L-W Lee, K-S Chu , et.al., VLSI Tech Digest, p.55, (2003)

2. Y-K Choi, T-J King and C. Hu, IEEE Trans. Electron Devices, 49, 3, p.435, (2002)

3. M. Belyansky in ‘Handbook of Thin Film Deposition”, 3^rd. Ed., K. Seshan Editor, Elsevier, p.46, (2012)