Current Status of Slurries and Cleans for CMP of III-V Device Fabrications – A Critical Review

With the growth of cloud computing market, the need for logic and memory chips for data centers have been steadily growing which require low power and high performance. Another area of growing semiconductor application is mobile products which require increasingly higher performance without sacrificing power.  The above two requirements can only be achieved by scaling supply voltage(V_dd).

III-V materials enable V_dd scaling to address power without sacrificing performance due to the very high electron injection velocity at virtual source compared to Si.  For example, V_inj (InGaAs) > 2V_inj (Si) at less than half V_DD.

 The development at Intel on InGaAs and at IMEC on Ge based FinFET structures have made it possible to conceive the integration scheme such as depicted in http://www.compoundsemiconductor.net/csc/features-details/19732136/Uniting-III-Vs-and-germanium-for-CMO.html .  

In order to enable such CMOS fabrication, development of CMP slurry, post CMP clean and modification of the  presently available process tools need to be done. While new slurries and cleans will be needed to planarize III-V film layer(s) without compromising the film composition (and functionality), modification of the process tool will be needed to address potential release of toxic waste water into the the waste stream after planarization.

At this time, published results show some academic works in addressing various issues related to CMP of III-V materials but there are not many reports in the public domain from the  industry to address the need which is essential to successfully integrate CMP as an enabling step in the manufacturing of III-V CMOS devices.

In this paper, the status of development of CMP processes, slurries and post CMP cleans will be reviewed and the critical needs to enable for the future III-V device integration will be analyzed.