(Invited) “Small Size” Effects in Si-Based Epitaxies for Advanced CMOS Technologies

Tuesday, 7 October 2014: 08:50
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
D. Dutartre, B. Seiss, D. Barge, and N. Loubet (STMicroelectronics)
Epitaxy (epi) is widely used in recent and advanced CMOS technologies for SiGe channels, SiGe stressors or raised sources/drains… and the device performances rely on the morphology and structure of these epitaxial layers. As deposition takes place in very small (10-40 nm) areas, we will see that physical mechanisms such as faceting, thermal rounding and agglomeration that strongly influence the final morphology cannot be ignored.


The first noticeable feature of epi or selective epi (SEG) is faceting [1]. This morphology has been demonstrated to be due mainly to kinetic considerations and not to equilibrium ones such as in Wulff construction [2].  The concept is that some (low index) planes present a smooth growth and the extension of these facets is determined by the relative deposition kinetics of these planes and by the configuration. Fig.1 illustrates the concept in the case of Si SEG between two walls. On the left, the SEM cross-section gives the epi morphology evolution owing to SiGe markers introduced during deposition. On the right, we have plotted the possible growth of different planes, and the transitory and the final morphologies are determined by the most limiting ones, i.e. {311} at high T (800°C).

Anisotropic Loading Effects.

When faceted SEG is realized in very small active areas, then with a significant vertical/horizontal aspect ratio, we have to introduce a new concept that has been named Anisotropic Loading Effects [3]. Indeed, considering as an example the case of <100> and <110>-oriented lines on (100) wafers, a similar deposition (same nominal thickness) gives rise to different morphologies and to different amounts of deposited material. The situation is illustrated in Fig.2. Depositions in <100>-oriented lines are limited by {100} facets and exhibit an important overgrowth whereas <110>-oriented ones are limited by {111} facets and with a very small overgrowth. Clearly, the amount of deposited material is not the same and if we define an effective thickness as the ratio between the deposited volume and the active area surface, <100>-oriented lines exhibit a growth rate much higher that the <110>-ones. Simple calculations with a <111> to <100> GR ratio of 0.32 led to the results given in Fig.3.

Thermal rounding

In first part, we mentioned that faceted epi does not correspond to equilibrium. This is illustrated in Fig. 4 where a SiGe SEG has been submitted to a moderate thermal budget: 30 sec at 637°C. Whereas the as-deposited morphology was fully faceted, like in Fig.2a, it is observed that the final morphology is very rounded; then, even very moderate thermal budgets can induce very important morphology changes. Indeed, very small objects are very sensitive to thermal rounding.

Pattern-induced stability/instability

Thermal rounding takes place in any small pattern and combines with other mechanisms such as SK instabilities in SiGe [4]. Taking the example of narrow lines on (100) wafers, we also discovered that this rounding is capable either to stabilize SK instabilities, either to induce new instabilities such as the Plateau-Rayleigh ones, and also that the morphology stability depends on the crystalline orientation. As an illustration, Fig. 5 shows AFM pictures of Si (a) and SiGe (b) epi in narrow lines; note that Si lines are instable whereas some SiGe lines are stable.

CMOS SiGe Channel

In recent “gate first” technologies (32-28 nm), SiGe is often used in <100>-aligned pMOS channels for threshold voltage (VT) and performances (hole mobility), and the epi has to be precisely controlled. In this context, we found that the as-deposited morphology was not suitable and that a certain epi rounding, as given in Fig.4, was able to optimize the control of  VT, to improve the driven current (effective width increase) and the technology yield (no parasitic stringer  present)

CMOS elevated Sources/Drains

FD-SOI technologies rely on ultra-thin channels and require raised sources/drains (RSD) to get a proper silicidation. However, this extra deposition also forms with the spacer and the gate electrode a parasitic capacitor that limits the commutation speed of the transistor. This effect can be reduced by changing the RSD epi morphology. Indeed, Fig.6 reports possible morphologies, and as indicated schematically, faceting (b) may be used to decrease this parasitic capacitor, as compared to a non-faceted one (a), and to produce more performing devices.

In the full paper, physics and integration will be detailed.


[1] L.Vescan et al. J. Vac. Sci. Technol. B 16(3) (1998)

[2] D. Dutartre et al, ECS meeting, 3(7), 473 (2006)

[3] D. Dutartre et al, Thin Solid Films 520, 3163 (2011)

[4] B. Seiss et al, Solid-State Electronics 83, 18 (2013)