Wet Processing for Post-epi & Pre-furnace Cleans in Silicon Carbide Power MOSFET Fabrication

Silicon carbide (SiC) power devices provide improved switching efficiency and are well-suited for high temperature, and medium to high voltage applications. As such, they are expected to spur growth for applications >1000V over the next decade as they enable significant reduction in emissions [1]. The chemically inert nature of SiC presents unique opportunities and challenges with regard to cleaning and surface preparation for fabrication of power metal-oxide-semiconductor field-effect transistors (MOSFETs).  SiC processing often leverages learning from ultra-large-scale integration (ULSI) Si, but exposing where that experience can be directly transferred or must be modified is part of the charter for the SiC fabrication community.  Here we present results for cleans post-epi test, also known as initial wafer clean (IWC), and prefurnace clean based on concentrated chemistries developed for Si, and discuss cost tradeoffs as the technology ramps from pilot to volume production. 

Although the diffusion of metals in single-crystal SiC is much slower than that found in silicon (Si) for similar temperatures, SiC thermal processing generally occurs at much higher temperatures and therefore metal contamination must be minimized to maintain process control and reliability. Iron, nickel, and other metallics are understood to degrade intrinsic lifetime of gate oxides, so are monitored for SiC processing at levels comparable to appropriate Si technology nodes.  W-anode TXRF is an effective diagnostic tool used in controlling these contaminants, so is employed by measuring Si and SiC monitor wafers run alongside device lots at appropriate process steps.  TXRF was performed at EAG in a Technos TREX model instrument.  Additionally, 1200V SiC MOSFETs are fabricated on epitaxially grown N- layers and typically characterized with mercury (Hg) probe capacitance-voltage (MCV), leaving trace levels of Hg on the SiC wafer surface.  In addition to the typical metal concerns, Hg must be removed before wafers proceed into the fabrication process flow.  For this study, 100mm SiC wafers were Hg probed in a Semilab MCV-530 tester, utilizing a multi-measurement pattern of 44 points.  Trace levels of Hg were analyzed with mapping-mode Mo-anode TXRF before and after a variety of cleans to provide a basis for comparison. 

Concentrated ULSI Si cleans (SC1, SPM, DHF, etc) with appropriate station segregation were shown to be an effective surface preparation approach for both the prefurnace clean and IWC evaluations. Iron mapped with W-anode TXRF is often measured below 1e10 atoms/cm², representing control of Fe at or below levels identified by ITRS for Si nodes ~180nm [2], quite acceptable for the relatively thick gate oxides (~50nm SiO₂) and critical feature sizes required in power semiconductor fabrication.  For the IWC study, mapped Hg levels measured with Mo-anode TXRF on SiC were shown to be reduced from a typical average value of 2.5e14 atoms/cm², and typical maximum value of 2.4e15 atoms/cm² immediately after post-epi test, to levels below the 300-second detection limit of 7e10 atoms/cm².  In the extended paper we will discuss prefurnace cleans in the context of control charting for pilot volume manufacturing, and compare a variety of cleans at IWC; including dilute mixtures, to evaluate improvements in cost effectiveness through reduction of chemical consumption and environmental impact. 

Research was sponsored by the NY Power Electronics Manufacturing Consortium. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of NY Power Electronics Manufacturing Consortium or the state of New York.

[1] E. Vivrey, “Wide Band Gap Power Electronics: A Path Toward CO₂ Emission Decrease”, Semicon West TechXPOT, July 10^th, 2014.

[2] International Technology Roadmap for Semiconductors, 2000 Update, Front End Process, http://www.itrs.net