(Invited) Bringing III-Vs into CMOS: From Materials to Circuits

Tuesday, 30 May 2017: 10:40
Churchill B2 (Hilton New Orleans Riverside)
L. Czornomaz, V. V. Deshpande, E. O'Connor, D. Caimi, M. Sousa, and J. Fompeyrine (IBM Zurich Research Laboratory)
High-mobility channel materials such as InGaAs and SiGe alloys are considered to be the leading candidates for replacing strained Si in future low power/high performance logic circuits. However, the integration of InGaAs on Si and the co-integration of InGaAs devices with SiGe devices are extremely challenging. On the one hand, the large lattice mismatch (8 to 10%) and the potential formation of antiphase domains at the polar/non-polar III-V/Si crystalline interface typically hinder the integration of high quality InGaAs crystals on Si. On the other hand, InGaAs and SiGe require very different processing conditions in terms of thermal budgets, dry and wet chemistries, passivation schemes and contacting schemes which complexifies the realization of CMOS circuits.

Recently, tremendous progress were achieved as a result of innovation at the material and device levels. Latest technology developments yielded the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line processes in a 2D co-planar configuration. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate.

Furthermore, progress on 3D Monolithic integration showed that this integration scheme not only an opportunity for further density scaling, but it also offers unique advantages for solving the integration of high mobility materials for 3D CMOS and stacking of functional layers on top of standard CMOS circuitry.