Today modern power device fabs are facing a variety of wafer sizes ranging from 100mm to 300mm, mainly depending on the availability of distinct base materials for power devices. For minimizing static and dynamic power losses of high voltage switches the main keys are local control of charge carrier lifetime and the use of thin and ultrathin wafers. Besides that, high dose implants with energies higher than the actually supported 60 keV to 80 keV on modern implanters are and will be necessary for source and p+ implantations in power devices.
In mainstream power technologies the main application driven key factors are lowest RDSon for compensation devices as well as minimal power dissipation for high voltage switches. Advanced in-situ metrology will be demanded for charge compensation devices of the next generation. The shrinkage of the pitch size and the related demand for a limitation of the lateral out-diffusion is driving the need for reliable energy stability as well as careful tuning of secondary process parameters. Implantations for material modification purposes are gaining relevance.
As of today the vast majority of power devices are still fabricated on silicon substrates. However, other semiconductors like SiC and GaN obtain superior material characteristics compared to silicon. That is why considerable development effort is put into the understanding of how to fabricate devices based on those materials. One ingredient is the knowledge how ion implantation can affect and tailor their semiconductor properties. An overview on effects of ion implantation into these materials will be given.
Overall, a summary of today’s challenges towards ion implantation for power device technology as well as an outlook to next generation demands will be presented.