Planar CMOS devices especially in 28nm and 20nm are currently the mostly used technologies for mass production microprocessors and SoC’s since it’s at an optimized spot of cost and performance. Over the last decades new processing techniques as well as new materials have been introduced such as strained Si, high-k metal gate and ultra-low-k. With the non-manufacturable arrival of EUV lithography integration techniques such as double and quadruple patterning, self aligned contacts; air-gap interconnects as well as new materials are needed for VLSI technologies of 7nm and beyond. 3D FinFET devices as well as new device architectures are required to continue an over-scaling in order to maintain the historical Moore’s Law to overcome the increased cost per gate. Simultaneously, the effort on variation reduction, performance and yield improvements increases exponentially for the design and manufacturing community. To keep pace with the technology over-scaling advanced techniques and solutions on the design and process integration as well as manufacturing processes are necessary. Reducing all parasitic resistances and capacitances is key for technologies below 7nm to gain in further SoC scaling while maintaining its performance level.
The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. The FDSOI technology is a real independent multi-gate technology which can span an infinite VTH space for any circuit design. In addition it’s well suited for low and lowest power applications as well as RF, mmWave, analog and mixed Signal SOC’s. Since it’s a planer technology, process and technology elements from previous nodes can be transformed into this novel architecture. With its diffusion less concept scaling is possible down to the 12nm technology node while maintaining the lowest cost trend by saving up to 30% fewer mask steps. The performance produces NFET (PFET) drive currents of up to 910μA/µm (856μA/µm) at 0.8V and 100nA/µm IOFF. For ultra-low power applications, it offers low-voltage operation down to 0.4V Vmin. Ultra-low leakage devices serve up to 1pA/µm IOFF and body-biasing can be used to actively trade-off power and performance. RF/Analog characteristics are achieved including high fT/fMAX of 375GHz/290GHz and 260GHz/250GHz for NFET and PFET, respectively. The high fMAX extends the capabilities to 5G and mmWave (>24GHz) RF applications.
Implementing an increased amount of sub-systems like graphic, video, TV, RF applications, sensor interfaces etc. challenges occur on I/O interface components and sub-system scaling. What once was 5-15% of a SoC die area is rapidly increased to 30-40% as the digital side over-scales in attempt to keep costs in line with Moore’s law. New 3D IC stacking technology concepts being introduced, which need to maintain the over-scaling and keeping the overall cost scaling on Moore’s Law historical trend line. Cost scaling can be enhanced with advanced methods on direct wafer boding, 3D-TSV or inductive coupling, which will come at a total power tradeoff, as the total combined die area will increase compared to a monolithic die. Continues innovation in area over-scaling and derivative technology approaches such as FDSOI will keep the current SoC’s scaling near the historic Moore’s Law trend to serve appropriate applications optimized in performance, power, and cost.