Argon Annealed ALD-ZrO2/SiON Gate Stack for Advanced CMOS Devices

Monday, 29 May 2017: 11:40
Churchill B2 (Hilton New Orleans Riverside)
R. Gupta (University of Jammu), D. Saikia (Sibsagar College, Joysagar, Assam, India), and R. Vaid (University of Jammu)
Now-a-days, high-k dielectric materials are in demand as they not only inhibit direct tunneling but also ensures relatively thicker oxides. To replace SiO2 as gate dielectric, a number of high-k materials have been extensively studied such as aluminum oxide (Al2O3), zirconium dioxide (ZrO2), cerium oxide (CeO2), hafnium oxide (HfO2) and titanium dioxide (TiO2). Among them, ZrO2 is one of the most outstanding candidates due to its excellent chemical, physical and electrical properties such as good thermodynamic stability with silicon, high dielectric constant, high melting point, high refractive index, and sufficient band gap. Atomic layer deposition (ALD) method having the benefit of low temperature deposition and extremely precise thickness control has been utilized for the deposition of ZrO2 film. Additionally, the post deposition annealing (PDA) of ZrO2in argon (Ar) ambient has been performed along with Ti-Pt as bilayer metal gate.

Taking into consideration the state-of-the-art research progress, we report the fabrication of ultra-thin silicon oxynitride (SiON) as a sacrificial layer (SL) for n-Si/ALD-ZrO2 gate stack followed by post deposition annealing (PDA) of ZrO2 in argon (Ar) ambient. The surface roughness for the Ar annealed ZrO2 film measured using atomic force microscopy (AFM) was found to be 0.796 nm whereas the thicknesses of SiON SL ~ 5.34 nm and ZrO2 film ~ 11.63 nm were corroborated by field emission scanning electron microscope (FESEM) and spectroscopic ellipsometer (SE). Electrical characterizations such as capacitance voltage and current voltage measurements indicates the improved results for n-Si/ALD-ZrO2/Ti-Pt MOS capacitor in terms of various performance parameters such as dielectric constant (K), effective oxide thickness (EOT), leakage current density (J), effective oxide charge (Qeff) and series resistance (Rs) and their determined values are 26, 2.1 nm, 8.75 × 10-9 A/cm2, 0.42 × 1013 cm-2 and 4.54 KΩ respectively. The noble concept of SiON SL along with the PDA of ZrO2 in Ar ambient can enable the further scaling of n-Si/SiON/ZrO2 gate stack without the adverse effects of gate leakage current. Some of the important results obtained from the reported work have been exemplified in the figures below.