For years, the effectiveness of the Damascene process has allowed the semiconductor industry to successfully keep the pace with the aggressive scaling of Moore’s law. However, ever increasing costs have raised the need for alternative technologies bringing advantages in terms of performance gain, time to market and cost competitiveness. Thus, 3D chip stacking technologies have now become a field of extensive research [1-2]. The today improvements are mainly devoted on the current process optimization or the development of new methods to elaborate barriers, seed-layers and fillings compatible with technological advances and the more and more aggressive via aspect-ratio [3]. Generally made in copper by CVD, PVD, ALD or electrografted technics, the seed-layer plays an important role during the via filling. Its principal criteria are to be uniform in term of thickness and continuous to ensure a good electrical contact during the electrochemical process [4]. During the filling process, the wafers and thus the seed-layer are first pre-wetted using DI water or etching solutions and then immerged in the copper bath. Traditionally an idle time is maintain before applying the current density, to favour the species exchange.

However, few studies have an interest for the reaction during this idle time and in more general consideration for the copper seed-layer stability on the copper electrolytic bath. Hence, the copper seed-layer is dissolved in the plating bath due to electrochemical reaction with the oxygen dissolved in the bath [5-7]. In this research work, the stability of the seed-layer and its dissolution rate are studied combining in-situ and ex-situ technics (figure 1). Open circuit potential versus time is an interesting approach for this study, allowing direct information on the surface modification during the idle time. Quartz microbalance measurements complete the analyses, giving direct information of weigh lost resulting from dissolution. As ex-situ characterization technics, SEM-EDS, XPS and RBS measurement were performed to characterize the surface states and the chemical composition after the idle time. Several parameters are particularly highlighted as the bath composition and its concentration and the rotation rate of the substrate.

[1] T.P. Moffat, D. Wheeler et al., IBM J. Res. Dev., 49, 19 (2005)

[2] P.M. Vereecken, R.A. Binstead, H. Deligianni, P.C. Andricacos, IBM J. Res. Dev, 49, 3 (2005)

[3] M. Datta, Electrochemical processing technologies and their impact in microelectronic packaging in Microelectronic Packaging, edited by M. Datta, T. Osaka and J.W. Schultze, CRC Press edition (2005)

[4] Part II Chip metallization in Microelectronic Packaging, edited by M. Datta, T. Osaka and J.W. Schultze, CRC Press edition (2005)

[5] R. Schumacher et al, J. Electroanal. Chem. 219 (1987) 311-3174

[6] K.Y. Electrochimica Acta, 38, 14 (1993) 2121-2127

[7] A.G. Zelinsky et al, Corrosion Science 46 (2004) 1083–1093