Wednesday, 4 October 2017: 08:00
Chesapeake C (Gaylord National Resort and Convention Center)
FinFET has been emerged as the leading device architecture for continuing CMOS scaling. It has entered mainstream CMOS manufacturing since 22nm node. In this paper, I will provide an overview on the challenges associated with CMOS scaling and articulate how FinFET circumvents those scaling challenges. Meanwhile, FinFET has its own unique issues related to device design and process integration. A detailed discussion on challenges and opportunities of FinFET will be discussed in detail. A general guidance for further scaling FinFET will be provided including channel materials, high-k/metal gate, strain techniques, device isolations. Advanced FinFET manufacturing techniques such as self-aligned multiple patterning and EUV lithography, selective epitaxy, and high-aspect ratio dielectric deposition will also be covered. Some common misconceptions about FinFET technology such as confusing technology node names adopted by different companies will be clarified. Finally, FinFET will be compared with other device architectures such as fully depleted SOI (FDSOI) and nanowire transistors. The advantages and drawbacks of each device architecture will be summarized.