(Invited) Low Power Tunneling FET Technologies Using Ge/III-V Materials

Wednesday, 4 October 2017: 08:30
Chesapeake C (Gaylord National Resort and Convention Center)
S. Takagi, D. H. Ahn, M. Noguchi, S. Yoon, T. Gotow, K. Nishi, M. Kim, T. E. Bae, T. Katoh, R. Matsumura, R. Takaguchi, and M. Takenaka (The University of Tokyo)
Low power consumption is one of the most important requirements for present and future integrated systems. Here, reduction in supply voltage is most effective in power reduction. Low supply voltage operation of charge-based logic switch devices can be achieved by steep slope devices with lower sub-threshold swing (S.S.) than CMOS. For this purpose, tunnel FETs (TFETs) have recently stirred a strong interest [1, 2], because of the high compatibility with CMOS platform. Here, materials with small and/or direct band gap such as III-V and Ge are preferred to enhance Ion of TFETs. In addition, type-II hetero-structures are known to be effective in boosting the TFET performance [1-3]. One of the critical technological challenges of pn-junction-based TFETs is the source junction engineering allowing us to form the source junctions with steep impurity profiles and low defect density for optimal Ge/III-V and/or hetero-interface materials. In addition, another key factor is low defect densities in the channel/junction regions and at the MOS interfaces. The MOS interface defects can include fast interface states, slow states and tail states near the band edges, while the reduction in the defect densities is not easy for other materials than Si. Thus, the channel and gate stack engineering for realizing defect-less structures are also quite important.

From the above viewpoints, we are currently working for the following material systems and source doping technologies [2-4], (1) InGaAs TFET with Zn diffusion source (2) GaAsSb (source)/InGaAs (channel) TFETs with Be in-situ doping (3) Ge (source)/strained Si (channel) TFETs with B in-situ doping. Here, Zn diffusion into InGaAs can automatically form pn junctions with steep Zn profile, because of the diffusion constant of Zn strongly dependent on Zn concentration [5, 6]. We experimentally confirmed the steep Zn profile and lower leakage current of InGaAs p-n junctions by solid phase diffusion from SOG films, attributed to the defect-less junction formation. Quantum-well InGaAs/InAs(3nm)/InGaAs n-TFETs with the Zn-diffused source regions and W/HfO2/Al2O3 gate stacks have exhibited the minimum S.S. value of 55 mV/dec and I60 (maximum source/drain current with S.S. less than 60 mV) of 0.7 nA/um at room temperature [3, 6].

In comparison with InGaAs homo-junction TFETs, III-V TFETs composed of type-II hetero-structures, GaSb/InAs and GaAsSb/ InGaAs, are expected to provide superior electrical characteristics, because of the smaller effective bandgap. We fabricated vertical n-TFETs using in-situ Be-doped p+-GaAs0.51Sb0.49/ In0.53Ga0.47As grown on InP by MOMBE [3, 7]. The steep Be profile of 11 nm/dec. is obtained, thanks to the in-situ doping of Be during the GaAsSb growth. We confirmed the operation of GaAsSb/InGaAs TFETs through observation of the negative differential resistance under forward bias condition. However, high leakage current attributable to defects in the source junction significantly degrades the performance at 297 K. The characteristics at 20 K with S.S. of 82 mV/dec. are regarded as the TFET performance dominated only by tunneling.

Another type of type-II hetero-interface n-TFETs has been realized by p+Ge/strained SOI structures [3, 4, 8, 9]. Here, higher valence band edge of the source due to Ge and lower conduction band edge of the channel due to bi-axial tensile strain are combined to form the type-II band line-up. p+Ge/SOI with tensile strain of 0.8 and 1.1 % were fabricated by using bi-axial strained SOI substrates and in-situ B doping during Ge MBE growth. The higher Ion and lower S.S.min were obtained by applying tensile strain. The unstrained, 0.8 and 1.1 % strained SOI TFETs after 400 oC PMA [9] yield S.S.min of 69, 48 and 29 mV/dec. and Ion/Ioff of 4.4, 2.2 and 3.7x107, respectively, at room temperature.

This work has partly been supported by JST-CREST. The authors would like to thank Drs. M. Yokoyama, O. Ichikawa, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, Drs. M. Mitsuhara, H. Sugiyama, Hoshi and H. Yokoyama in NTT for their collaborations.

References [1] A. C. Seabaugh et al., IEEE Proc. 98, 2095 (2010) [2] S. Takagi et al., Symp. VLSI Tech., T22 (2015) [3] S. Takagi et al., IEDM, 516 (2016) [4] S. Takagi et al, Solid State Electron. 125, 82 (2016) [6] S. Takagi et al, IEDM, 516 (2016) [5] M. Noguchi et al., J. Appl. Phys. 118, 045712 (2015) [6] D. H. Ahn et al., Symp. VLSI Tech., 224 (2016) [7] T. Gotow et al., SSDM, 21 (2016) [8] M. Kim et al., Thin Solid Films 557, 298 (2014) [9] M. Kim et al., IEDM, 331(2014)