The heavy ion induced response in Tunnel FET (TFET) is discussed by comparing to that in conventional MOSFET using device simulation. It was confirmed that both shorter transient current pulse and smaller collected charge were observed in TFET due to suppression of the parasitic bipolar effects.
One of the detrimental problems with CMOS devices in radiation environments, such as space and around the nuclear reactors, is single event phenomena (SEP). When a high-energy particle irradiates to the device, electron-hole pairs are generated along the ion-track by ionization effect, and they can create a sufficient transient current to cause an incorrect device response (single event transient). Silicon-on-insulator (SOI) technology had been developed to reduce SEP, because the sensitive region was limited to the individual transistors isolated from the substrate. However, the reliability issue is more sensitive on a higher performance CMOS device with the small device size, thin active region and lower applying voltage1). In case of conventional n-type SOI-MOSFET, the generated electrons in channel region are drifted to drain region by applying drain bias. However, the generated holes remain in the channel region due to the source/drain-channel barrier, and they degrade the source-channel potential barrier. Therefore the electrons in source region are injected to channel, and that creates a large current between source and drain. These phenomena are known as parasitic bipolar effects2). The effects are more enhanced in smaller size devices. In this study, we focused TFET as a radiation hardened device. The TFET has been developed to improve the sub-threshold slope, and is consisted by p-i-n type, as source-channel-drain region, with applying reverse bias. So it is expected that the radiation induced electrons and holes in channel region are drifted to drain and source, respectively, and that the parasitic bipolar effects can be reduced by TFET. We evaluated the heavy-ion induced transient current and collected charge in conventional FET and TFET, and also discussed the single event transient on TFET CMOS devices.
Simulation Model Figure (a) shows the cross section of the each SOI device, conventional MOSFET and TFET. We calculated heavy-ion induced transient current in these devices using a 2D device simulator. We set the heavy-ion with the LET of 10 MeVcm2/mg strikes to the center of the channel region in each OFF-state (VG = 0 V, VD = 1.5 V) device with normal incidence. In this case, the amount of radiation induced generation charge is 52 fC in the active layer (SOI region).
Figure (b) shows the simulated results of transient current and collected charge, the time integral of the current, of each device. On the results of conventional MOSFET, the decay rate of transient current is much slower than the TEFT, and it is confirmed that the amount of collecting charge is saturated with about 500 fC, about 10 times as much as generated charges. It is considered that the phenomena are caused by the parasitic bipolar effect. On the other hand, in TFET device, the transient current reduces steeply and the collected charge is saturated with the same value of generated one. From these results, it was confirmed that the radiation induced collected charge can be reduced significantly using TFET. We also evaluated the change of band diagram in each device with time after irradiation. In the results of conventional MOSFET, the source-channel potential barrier is changed to almost zero by irradiation due to the holes stored in the channel region. In the case of TFET, it is found that the band diagram in not changed by irradiation. That indicates the generated electrons and holes can escape rapidly from the channel region due to the asymmetric source/drain doping structure in TFET. From these results, we confirmed that the parasitic bipolar effects could be eliminated using TFET.
This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc.
1) P. E. Dodd, et al.,”SEU-Sensitive volumes in Bulk and SOI SRAMs From First-Principles Calculations and Experiments” IEEE Trans. Nucl. Sci., Vol. NS-48, pp. 1893-1903. (2001)
2) V. Ferlet-Cavrois, et al., “Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs” IEEE Trans. Nucl. Sci. Vol. 53, No. 6, pp. 3242-3252. (2006)
3) D. Kobayashi, et al., “Analytical Expression for Temporal Width Characterization of Radiation-Induced Pulse Noises in SOI CMOS Logic Gates” in proceedings of IEEE CFP09RPS-CDR 47th Annual International Reliability Physics Symposium, Montreal (2009)