The more adaptable and more intimate is this heterogeneous integration between two or more technologies, the more flexibility is given to the designer for the selection of the technology for a specific function, or even better, for an optimum combination of different transistor technologies in the same function or cell in the design. Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing heterogeneous integration processes, design kits and thermal simulation tools to integrate submicron CMOS, InP HBT, GaN HEMT and high-Q passive technologies for advanced DoD and other government systems. We have demonstrated integration of NGAS’ TF4 and TF5 InP HBT and GaN20 GaN on SiC HEMT technologies on IBM’s 65nm CMOS and GlobalFoundries’ (GFUS) 45nm CMOS (12SOI).
The NGAS DAHI integration process has several advantages. It is scalable to 200 mm and 300 mm CMOS wafers and fully compatible with all Si technologies. All the technologies to be integrated are independently fabricated in parallel for optimum cycle time and decoupled line yield. The NGAS DAHI integration approach also offers advantages from the thermal management point of view. The low thermal resistance heterogeneous interconnects (HICs) enable flexible electrical and thermal routing. The GaN HEMT is integrated with its backside facing the CMOS front side to allow better intra-chip heat spreading and large inter-chip HIC heat sink arrays. The thickness of the Silicon Carbide (SiC) substrate in the GaN HEMT chiplet is designed to be thick enough to allow optimum lateral heat spreading before reaching the thermal HIC interface. The TF InP HBT technology is integrated with its front side facing the CMOS front side for maximum density of interconnects. An additional important task in the development of the DAHI technology is the creation of an integrated DAHI process design kit (PDK). The objective of the DAHI PDK development is to have a flexible design environment that can accommodate schematics, layouts and simulations of integrated DAHI circuits with device-level integration designs of a wide variety of technologies. Integration circuit results will be presented at the conference.
This work is supported by DARPA DAHI Program under AFRL contract No. FA8650-13-C-7312, Daniel Green DARPA program manager and Robert Fitch AFRL COTR. The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government.