The continuous scaling of CMOS devices requires new process developments because of the strong reduction of the allowable thermal budget for device processing. This is especially the case for narrow FinFET structures and vertically stacked MOSFET devices. New epitaxial growth schemes using higher order precursors are being assessed to enable epitaxial growth at the required reduced growth temperatures. An example is the epitaxial Si growth on narrow Ge fins to passivate (strained) Ge surfaces in the high-k gate module [1-3]. The benefit of the Si passivation layer over GeO_x-based gate stacks is its potential to improve Bias Temperature Instability (BTI) reliability. During the epitaxial Si growth Ge surface segregation needs to be avoided as it leads to an increase of the interfacial trap density and distribution in the final gate stack. On the other hand, the Si passivation layer has to be sufficiently thin to approach an Equivalent Oxide Thickness (EOT) close to 1 nm and below as implemented in the current 14 nm-node FinFET. If the Si passivation layer is grown on strained Ge FinFET structures, there is a risk for Ge surface reflow during the Si deposition. This in turn would lead to a (partial) relaxation of the strained Ge layer [1,3]. The requirement for extremely low process temperatures during epitaxial Si growth (£ 450 °C) sets the need to use higher order Si-precursors such as Si₃H₈ or Si₄H₁₀. Despite the use of these higher order precursors it is challenging to avoid the surface reflow of compressively strained Ge, especially for narrow fins [1,3].

In this contribution, we will discuss epitaxial Si growth by means of CVD at temperatures down to 330 °C and using tetrasilane (Si₄H₁₀) as Si precursor. Replacing Si₃H₈ by Si₄H₁₀results in ~40% higher growth rates. The growth rate also depends on the choice of the carrier gas and is affected by the underlying virtual substrate [2]. The Si growth characteristics are discussed in view of the use for Ge surface passivation in the high-k gate module [4-6]. We use relaxed Ge fins for nFINFET devices and compressively strained Ge epitaxially grown on SiGe virtual substrates for pFINFET devices [1,3]. The deposition of the Si passivation layer on relaxed or compressively strained Ge FinFET structures is expected to be conformal as the extracted growth rate is very similar for (001) and (110) surfaces. For the given Si growth conditions, Ge segregation into the Si epi layer is supressed as confirmed for Si growth on blanket virtual substrates. CV characteristics of blanket capacitors made on such Ge virtual substrates point to the presence of an optimal Si thickness. In case of strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. The non-uniform strain is caused by the extremely large lattice mismatch between the Si passivation layer and the Ge fin. Using atomistic modelling, the strain levels in the compressively strained Ge have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for eventual Ge surface reflow during the Si deposition. The unwanted Ge surface reflow is reflected in a reduction of the compressive strain as measured by HR-XRD. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.

Acknowledgements:

The imec core CMOS program members, European Commission, local authorities and the imec pilot line are acknowledged for their support. Epi layers are grown in Epsilon^TM3200 and Intrepid^TMXP systems from ASM. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases and Bruker Semiconductor Division for their kind support in XRD characterization of high mobility materials implemented in complex device architectures.

References:

[1] J. Mitard et al., 2016 Symposium on VLSI Technology, Digest of Technical Papers, p. 34

[2] R. Loo et al. accepted for The 10th Int. Conf. on Silicon Epitaxy and heterostructures (ICSI10)

[3] R. Loo et al. ECS J. of Solid State Sci. Techn., 6 (1) P14-P20 (2017)

[4] H. Arimura et al., IEEE Int. Electron Dev. Meeting (IEDM), Tech. Dig., p. 588 (2015)

[5] H. Arimura et al., IEEE Int. Electron Dev. Meeting (IEDM), Tech. Dig., p. 834 (2016)

[6] H. Arimura et al. accepted for 2017 Symposium on VLSI Technology