(Invited) Sequential 3D Process Integration: Opportunities for Low Temperature Processing

Tuesday, 3 October 2017: 14:30
Chesapeake C (Gaylord National Resort and Convention Center)
S. Kerdilès (Univ. Grenoble Alpes, CEA, LETI, 38000 Grenoble, France, Université Grenoble Alpes, Grenoble, France), P. Acosta-Alba (Université Grenoble-Alpes, CEA-LETI, Université Grenoble Alpes, Grenoble, France), B. Mathieu (CEA-LITEN, Grenoble, France, Université Grenoble Alpes, Grenoble, France), M. Veillerot, H. Denis, F. Aussenac (CEA-LETI, Grenoble, France, Université Grenoble Alpes, Grenoble, France), F. Mazzamuto, I. Toque-Tresonne, K. Huet (SCREEN-LASSE, Gennevilliers, France), M. P. Samson (STMicroelectronics, Crolles, France), B. Previtali, L. Brunet, P. Batude, and C. Fenouillet-Beranger (CEA-LETI, Grenoble, France, Université Grenoble Alpes, Grenoble, France)
3D sequential integration of two stacked transistor levels has been recently demonstrated with success on 300 mm wafers with a maximum thermal budget approaching 650°C-20 minutes for the completion of the top level [1]. However, such thermal budget is still too high to avoid any degradation of the bottom transistors performance [2]. Thus, for several technological modules, such as dopant activation, gate stack formation, spacers deposition and source/ drain epitaxy, very low temperature processes must be developed. For low temperature junction activation, solid phase epitaxy regrowth (SPER) is a first option, with typical annealing conditions around 600°C-1 minute [1]. Sub-microsecond laser annealing is a second approach, with the capability to selectively heat a sub-µm surface region. In this paper, we review recent advances in UV pulsed laser annealing in view of 3D sequential integration.

Based on 2D numerical simulations, we optimized the process structure for the upper source and drain activation and recrystallization upon laser annealing (wavelength: 308 nm), while trying to avoid any degradation of the bottom transistor. An anti-reflective capping layer over the top transistors is found to reduce laser energy absorption in the upper gate (Figure 1). The lower gate maximum temperature can be reduced down to 600°C (pulse duration: 160 ns) with a structure combining favorable bottom BOX and inter-level SiO2 thicknesses (Figure 2). Moreover, with a shorter laser pulse (80 ns), the bottom level temperature can even approach 500°C while the upper level layers reach 1200°C.

To mimic the optimal structures with simple vehicle tests and evaluate the laser annealing process window for dopant activation, SOI structures (25 nm BOX, 23 nm top Si layer) have been implanted with As, BF2 or P, then capped with 30 nm SiN and annealed using SCREEN-LASSE LT-3100 system at various laser energy densities. Sheet resistance measurements combined with SIMS profiles and TEM cross-section observations (Figure 3) allowed us to identify the different regimes encountered as a function of the laser fluence. The process window starts when the whole region amorphized by implantation on top of the single crystalline thin seed layer is melt, and stops with the full SOI layer melt. Around the optimal energy density, we reached perfect crystal recovery and high dopant activation levels, comparable to those obtained with spike RTP. Concerning the laser pulse duration, a trade-off is to be found: The process window is reasonably large in case of a 160 ns pulse and becomes narrower with a 80 ns pulse but such shorter laser treatment is more favorable in terms of heat diffusion.

To avoid global routing congestion, the 3D sequential architecture requires the introduction of inter-tier Back-End-Of-line (iBEOL) levels routing the bottom tier. As a consequence, such iBEOL needs to support the thermal budget applied for the top tier processing. Coupling numerical simulations with experimental tests on simplified structures, we investigated the impact of pulsed laser annealing on such inter-level metal interconnection. Based on 28 nm standard design rules, we integrated one metal level (Cu) using porous SiOCH as ultra-low-k dielectric and the appropriate barrier layers. Before submitting such structures to laser annealing, we deposited 50 nm or 120 nm inter-level SiO2 and 20 nm amorphous Si (a-Si) to simulate the top transistor level. According to simulations, above relaxed interconnect regions (large interconnect pitch), the average thermal conductivity of the stack is lower, promoting a slightly faster temperature rise in these regions, compared to more dense regions. A thicker inter-level oxide layer contributes to reduce the peak temperature of the Cu interconnects. Finally, line resistance and lateral capacitance measurements show no modification upon laser annealing, even with conditions leading to the melt of the top a-Si layer, for both 50 and 120 nm inter-level oxides (Figure 4).

All these results provide guidelines for low temperature junction formation in a 3D sequential integration using nanosecond laser annealing, reinforcing this technique as a true alternative to SPER.



[1] L. Brunet et al., Proceedings of symposium on VLSI Technology (2016) 7573428.

[2] C. Fenouillet-Béranger et al., Proceedings. of Intern. Electron Devices Meeting (2014) 7047121

[3] C. Fenouillet-Béranger et al., Proceedings of SOI-3D-Subthreshold Microelectr. Technol. Unified Conf. (2016) 7804375

[4] P. Acosta-Alba et al., Proceedings of. Ion Implant. Technol. Conf. (2016)

[5] S. Kerdilès et al., 16th Intern. Workshop on Junction Technol. (2016) p.72