The device is fabricated by the process described in Fig. 1 using the following steps: (a) an aluminum wiring layer is formed in a SiO2 dielectric layer on a Si substrate; (b) first via holes are formed on the surface of the SiO2 layer and are embedded with electroplated Au; (c) an Au/SiO2 bonding surface is formed by chemical–mechanical polishing (CMP), and the wafer is diced into the top-, middle-, and base-layer chips; (d) the bonding surfaces of the top- and middle-layer chips are activated by O2 plasma; (e) the top- and middle-layer chips are directly bonded by applying a force of 20,000 N for 60 min at 330 °C; (f) the Si substrate of the middle-layer chip is removed by grinding and XeF2 vapor-phase etching; (g) second via holes are formed on the exposed backside of SiO2 of the middle-layer chip and are embedded with an electroplated Au; (h) an Au/SiO2 bonding surface is formed on the backside of the middle-layer chip by CMP; (i) the bonding surfaces of the middle- (backside) and base-layer chips are activated by O2 plasma; and (j) the bonded (top- and middle-layer) chip and the base-layer chip are directly bonded by applying a force of 20,000 N for 60 min at 330 °C. Figure 2 shows a cross-sectional scanning electron microscopy (SEM) image of the three-layered daisy-chain test device. No voids were observed at the two bonded interfaces. Details of the three-layered stacking process and experimental results will be discussed in the presentation.
1. M. Goto et al., IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3530–3535, (2015).