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Three-Layered Stacking Process by Au/SiO2 Hybrid Bonding for 3D Structured Image Sensors

Tuesday, 3 October 2017: 15:00
Chesapeake C (Gaylord National Resort and Convention Center)
Y. Honda, M. Goto, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi (NHK Science and Technology Research Laboratories), T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, and T. Hiramoto (The University of Tokyo)
A 3D structured CMOS image sensor is investigated wherein two layers (photodiode array layer and signal processing circuit layer) are stacked using a low-temperature Au/SiO2 hybrid bonding technique [1]. We previously reduced the pitch of Au electrodes from 40 μm to 6 μm and confirmed that the Au electrodes could be electrically interconnected via the bonding technique [2]. To further enhance its performance, higher integration by multilayer stacking is essential. Therefore, we developed a multilayering technique by direct bonding and manufactured a three-layered daisy-chain test device to examine the numerous interconnections.

The device is fabricated by the process described in Fig. 1 using the following steps: (a) an aluminum wiring layer is formed in a SiO2 dielectric layer on a Si substrate; (b) first via holes are formed on the surface of the SiO2 layer and are embedded with electroplated Au; (c) an Au/SiO2 bonding surface is formed by chemical–mechanical polishing (CMP), and the wafer is diced into the top-, middle-, and base-layer chips; (d) the bonding surfaces of the top- and middle-layer chips are activated by O2 plasma; (e) the top- and middle-layer chips are directly bonded by applying a force of 20,000 N for 60 min at 330 °C; (f) the Si substrate of the middle-layer chip is removed by grinding and XeF2 vapor-phase etching; (g) second via holes are formed on the exposed backside of SiO2 of the middle-layer chip and are embedded with an electroplated Au; (h) an Au/SiO2 bonding surface is formed on the backside of the middle-layer chip by CMP; (i) the bonding surfaces of the middle- (backside) and base-layer chips are activated by O2 plasma; and (j) the bonded (top- and middle-layer) chip and the base-layer chip are directly bonded by applying a force of 20,000 N for 60 min at 330 °C. Figure 2 shows a cross-sectional scanning electron microscopy (SEM) image of the three-layered daisy-chain test device. No voids were observed at the two bonded interfaces. Details of the three-layered stacking process and experimental results will be discussed in the presentation.

1. M. Goto et al., IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3530–3535, (2015).

2. Y. Honda et al., ECS Trans., vol. 75, no. 9, pp. 103–106, (2016).