As technology nodes continue scaling, it is more cost- effective to integrate all SoC building blocks onto a single chip. On-chip BEOL compatible Metal-Insulator-Metal (MIM) decoupling capacitors have attracted increasing interest. They are placed close to the power lines to reduce high frequency noise. Recently there has been great progress on the development of high density (>20fF/μm²) BEOL compatible MIM capacitors. However, no report has been published on the complexity of incorporating such MIM capacitors into the full integration scheme. It is known that multi-level Si structures combined with certain chip design can create topography issues, which will in turn cause a significantly narrowed process window for multiple processes. Addition of high density MIM capacitors will further generate complex effects on both MIM capacitor performance and Cu interconnections. It is imperative to have robust solution for high volume and foundry manufacturing.

MIM capacitors are often integrated between the last two Cu layers, as illustrated in Fig. 1. Bottom and top electrodes are TiN, and High k is HfAlO. Etch processes are used to pattern the capacitors, followed by oxide deposition and a CMP process to planarize the patterned topographies. Fig. 2 (a) illustrates the natural topographies produced by MIM capacitor patterning processes. The step height post MIM patterning can be more than 100nm. Without proper polish, this natural topography cannot be completely planarized. Fig. 2 (b) illustrates the remaining natural topography with insufficient polishing.

In addition, design-related pattern density non-uniformity causes localized topographic weak points. These weak points will add further complexity and reduce process window needed to accommodate both MIM capacitors and Cu interconnections. The related fail modes include shorted Cu lines above MIM capacitors, unlanded Cu interconnection vias, and even punch-through of MIM capacitors, as shown in Fig. 3 (a), (b), and (c), respectively.

The oxide thickness post MIM polish has to be properly controlled to accommodate both the need to planarize MIM topographies and the need for MIM capacitor functioning. Fig. 4 (a) shows the polish rate change as a function of polish time. As polish time increases polish rate gradually decreases over a transition period, and then stabilizes at ~75% of the initial value, indicating the natural MIM topographies have been planarized. RMS roughness is reduced by more than 80% (see Fig. 4 (b)).

Through sufficient and optimized MIM polish, MIM topographies as well as MIM capacitor performance are greatly improved. Fig. 5 demonstrates the process robustness with planarized MIM topographies and proper oxide thickness. All three types of vias are formed properly, that is, vias landing on MIM top electrode (Via I), on MIM bottom electrode (Via II), and on lower level Cu (Via III). Electrical characterization (Fig. 6) also shows that with an optimized oxide polish process, MIM degradation is fully recovered. High volume manufacture of MIM capacitors with capacitance density >20fF/μm², leakage current density <100nA/cm², and breakdown voltage > 5V is demonstrated in production.

In summary, we have demonstrated high density MIM capacitors, fully integrated in an advanced BEOL process, and shown a thorough study of their topographies and the complex impacts. An optimized planarization process was developed to enable both MIM capacitors and Cu interconnections. The process robustness was demonstrated for such capacitors that deliver capacitance density above 20 fF/um², leakage current density below 100 nA/cm² at 1.45V, and breakdown voltage above 5V. The results greatly facilitated high volume and foundry manufacturing capability of such on-chip high density BEOL MIM capacitors.