Deep Trenches Cleanliness Challenges for CMOS Image Sensors

Monday, 2 October 2017: 15:00
Chesapeake I (Gaylord National Resort and Convention Center)
P. Garnier, F. Dignat (STMicroelectronics), and C. De Buttet (CEA-LETI)

Deep trenches are widely used, either as capacitors in memories, or as electrical / optical isolation between two transistors or pixels in CMOS integrated circuits or CIS(CMOS Image sensors). Therefore, their isolation quality depends on their cleanliness, and the processes to define such structures are extremely critical.

First and foremost, DTI(Deep Trench Isolation) are usually passivated with P type dopants. This prevents electrons from getting from one pixel to the next one. Therefore this doping integrity must be kept and no counter doping pollution must be introduced. Unfortunately, during the DTI formation, a silicon nitride step is used to help defined the structure. And standard used chemical to etch such material is phosphoric acid, hence a potential source of phosphorous counter-doping. This paper shows prooth of such contamination in both cases of H3PO4 use with non-optimized but conventional rinse. First, CIS device malfunctions has been evidenced due to deep trenches failure at electrical testing. Reverse engineering did show both phosphorous and carbon contamination (figure 1). The first one comes from a wet bench with a H3PO4 unefficient rinsing, and the carbon condensation from the IPA Marangoni like wafer drying. These both defects are trapped inside extremely thin voids / seams of the deep trenches, and not removed afterwards. Same behavior has been observed on a spin dry single wafer tool with H3PO4 dispense, with a too mild rinse and SC1 (Standard Clean 1), leading to a total failure of the CIS device (figure 2). In order to prevent such phenomena, best is to use an alternative process, based on a hot ultrad diluted HF process (figure 3) [1]. Not only one has not to take care about the counter-doping dilemma, but also due to the extreme dilution, the rinsing is quite easy, and tremendous CIS performance improvement is reached. Probably thanks to the use of fresh chemicals, preventing any metal contamination from recirculated chemicals.

A second discussion about the DTI cleanliness improvement will take place, dealing with the metal cleaning efficiency inside these high aspect ratio features. Before studying the metal contamination removal, inside deep trenches, a special focus on the wetting of these structures has been done [2][3]. Then intentional ions contamination inside deep trenches has been validated. This method is well managed on flat surfaces but never validated inside high aspect ratio features. IPA and deionized water solutions with ions intentional contamination have been compared (figure 4). A pure IPA generates a higher contamination level than water. Similar behavior has been observed in DTI structures. TXRF has been used for blanket surfaces, and tof SIMS for DTI (figure 5). An excellent uniformity of the ions contamination has been found inside the trenches.

Eventually a discussion about metal ions removal efficiency results will show adequate process sequences required to best clean high aspect ratio structures.

[1] P.Garnier, Silicon Nitride Etch – an Alternative to Orthophosphoric Acid, ECS Transactions 69(8):169-175 · October 2015

[2] C.Virgilio, Deep trench isolation and through silicon via wetting characterization by high frequency acoustic reflectometry

[3] M. Olim, Liquid-Phase Processing of Hydrophilic Features on a Silicon Wafer, J.Electrochem. Soc. , Vol. 144, N°12, Dec 1997