For the manufacturing of Si-based semiconductors, CMP is utilized extensively to enable FEOL process integration such as STI, deep-trench, ILD, and poly-open. Silica slurries are usually adopted for bulk oxide polish while ceria slurries are more suited for the final “buff” polish where high selectivity to nitride is required. The ever stringent requirement for scratch reduction leads to the trend of using nano-sized abrasive particles in all types of CMP slurries. However, the stronger adhesion force between these nanoparticles and wafer surface necessitates the re-design and optimization of post-CMP processes to meet the low PR/FM defect requirement.

The selection of proper chemicals is often the first step towards post-CMP cleaning. However, design of cleaning sequence, exploitation of the tool hardware, and optimization of operating parameters are equally critical to achieve maximum cleaning efficiency. As shown in Fig. 1, for an oxide or poly-Si CMP process with an acidic silica-based slurry, a preferred post cleaning process should operate in alkaline environment (e.g., pH 8~10) in order to build in repulsive zeta potential for easy of particle removal from wafer surface.

In this case, the use of an acidic pCMP chemical would be unfavorable from zeta-potential point of view. Replacement of acidic chemical with just DIW (pH ~ 7) leads to significant reduction in PR/FM. In addition, optimization of the directionality, spin rpm, arm oscillation speed…etc, helps eliminate the wafer center-heavy signature and reduces the defect count further down.

For FEOL CMP with ceria-based slurry running on a 3-platen polisher with serial meg tank/brush cleaning module, one can design the pCMP process based on the unique “reactive” nature of ceria abrasives, and also fully exploit the available hardwares and their process parameters. In this example, the POR process adopts only DIW in the meg tank. The go-to process, however, replaces DIW with a diluted acidic oxidizer so as to neutralize the reactive ceria abrasives, making it much easier to dislodge the particles from oxide wafer surface.

The significant FM NADD reduction with the go-to pCMP process illustrates the efficiency of adding the meg clean step with diluted oxidizer. Further PR/FM reduction can be realized by optimizing the hardware and machine parameters such as those listed in Fig. 2, from on-platen buff clean all the way to the terminal step of Maragoni drying. Furthermore, for a new pCMP process to be considered production-ready, run order effects, repeatability, and CoO reduction need to be taken into account as well. In addition, post-clean surface analyses are carried out to ensure no potential reliability concern.

Reference:

W.-T. Tseng, J. Hagan, K. Mohan, R. Hull, J. MacDougall, R. Murphy, L. Tai, S. Molis, “Post Cleaning and Defect Reduction for Tungsten Chemical Mechanical Planarization” ICPT, 2015.