Wafer charging becomes an increasingly important issue, thus being a key parameter in 10 nm and sub-10 nm technology nodes. Single-wafer cleaning equipment has various advantages over batch-type processes, and adoption has been widespread in both BEOL and FEOL manufacturing. Since the process module is constructed primarily of plastic for chemical compatibility, there are significant challenges in managing charge build-up to an acceptable level.

Amongst known charging failure modes, an arcing event is the most destructive toward device yield. Hagimoto, Matz, and Halladay discovered that cleaning chemistries with different conductivity and film stacks generate different types of punch-through defects on the wafer surface. Dielectric layers such as SiO₂ and Si₃N₄ are where these charges accumulate. Typically these charges could be dissipated by Ionized CO₂ Water (DI-CO₂) [4, 5, 6]. However, 10 nm BEOL processes have a very tight specification on Cu film loss, limiting the use of DI-CO₂. Hayashi et al. reported that dilute NH₄OH has lower Cu etch rate than does DI-CO₂and also has high discharge capability [7].

In this study, a different approach is investigated. A vacuum ultraviolet (VUV) lamp is used to dissipate charge generated in a de-ionized water (DIW) single-wafer clean process.

Experimental

A VUV lamp (wavelength ~200-nm) is used on wafer discharging. 1,000 Å thermal oxide wafers were processed with DIW-only at 200 rpm, 60s, and 1 lpm flow with center dispense. Charging profiles were measured on a Qcept metrology tool.

Results

Figure 1 shows the effect of VUV discharging. The solid lines represent typical wafer charging by a DIW process. The thermal oxide wafer is negatively charged at the center. This is because of DIW tribo-electric charging effects from the DIW dispense at the center of the wafer. At the wafer edge, the process generates positive charge. The mechanism is correlated with the center-negative charging. When Si-OH at the center is negatively charged, H+ ions are generated; these spin out from the wafer center and accumulate at the wafer edge. In Figure 1a, the VUV lamp is located at the wafer center, and the post-VUV exposure charging profile is changed from -10V to 0V (broken lines). In Figure 1b, the VUV lamp is located at the wafer edge, and it also shows from +4V to 0V discharging. Two sets of data suggest that VUV can neutralize both positive and negative charges.

In order to understand if there is any negative impact of VUV exposure, k-value shift of the dielectric film is measured. In Table 1, k-values are compared for different wafer locations – center, middle, and edge. The VUV nozzle is scanned from center to edge. The results are normalized to reference data with no VUV exposure. The center area showed a severe k-value shift with prolonged exposure time. This means that optimized exposure is needed to minimize damage due to VUV.

Additional damage studies and optimized VUV scan profile will be introduced in the conference.

<align="left">(a) (b)

Fig. 1: VUV discharge effects: (a) wafer center-negative charges are dissipated, (b) wafer edge-positive charges are dissipated.

Table 1: Low-k film k-value shift after VUV exposure.

By zone	VUV 10s (normalized)	VUV 120s (normalized)	VUV 600s (normalized)
Center	1.19	1.35	1.91
Middle	1.03	1.06	1.08
Edge	1.02	1.03	1.01

References

[1] D. S. L. Mui, E. H. Lenz, C. Cyterski, K. Venkataraman and M. Kawaguchi, IEEE Transactions on Semiconductor Manufacturing., 24, Issue 4 (2011), 552.

[2] Y. Hagimoto, H. Iwamoto, Y. Honobe, T. Fukunaga and H. Abe. Solid State Phenomena, 145-146, (2009), 112.

[3] M. Wada, T. Sueto, H. Takahashi, N. Hayashi and A. Eitoku, Solid State Phenomena, 134, (2008), 263.

[4] T. Guo, T. Tsai, C. Chien, M. Chan, C. Yang and J. Wu, Solid State Phenomena, 187, (2012), 63.

[5] J. Halladay, B. Teeter, R. Newcomb, W. Usry, J. Yoo, K. Lam, J. Lansford and B. Brennan, Proceedings of SPCC08, Austin, TX, April (2008).

[6] P Matz, T. Hurd, K. Cunningham et al., Proceedingsof the 212th ECS meeting, 7-10 October, (2007).

[7] Y. Hayashi, M. Kawakami, D. Yano and K. Yamanaka, ECS Transactions, 69 (8), (2015), 37.