Etching Methods for STT-MRAM

Tuesday, 3 October 2017: 16:20
Chesapeake C (Gaylord National Resort and Convention Center)
E. J. O'Sullivan (IBM Research Division, T.J. Watson Research Center), A. J. Annunziata (IBM Research Div., T.J. Watson Res. Center), J. Gonsalves (IBM Research Division, T.J. Watson Research Center), G. Hu (IBM Research Division, T.J. Watson Res. Center), E. A. Joseph (IBM Research Division, T.J. Watson Research Center), R. Kothandaraman, G. Lauer (IBM Research Division, T. J. Watson Research Center), N. Marchack (IBM Research Division, T.J. Watson Research Center), J. J. Nowak (IBM Research Division, T. J. Watson Research Center), R. P. Robertazzi (IBM T.J. Watson Research Center), J. Z. Sun (IBM Research Division, T. J. Watson Research Center), T. Suwannasiri (IBM Research Division, T. J. Watson Research Center,), P. L. Trouilloud (IBM Research Division, T.J. Watson Research Center), Y. Zhu, and D. C. Worledge (IBM Research Division, T. J. Watson Research Center)
Spin-transfer torque [1] MRAM (STT-MRAM) continues to be the subject of intense investigation due to its scalability and excellent endurance. Initially explored mainly as a DRAM replacement, STT-MRAM with perpendicularly magnetized materials is now targeted as a nonvolatile memory, medium-performance replacement for mobile applications, and more long term as a fast, dense, cache memory. This talk will review MRAM magnetic stack etching methods and related aspects of integration, with particular reference to STT-MRAM.

An STT-MRAM memory cell, which consists of a magnetic tunnel junction (MTJ) and a transistor, has the attractive property that if the critical current density for spin-torque switching (Jc) remains constant, then the critical current for MTJ switching (Ic) will scale as λ2, where λ is MTJ diameter . Thus, scaling is highly desirable for STT-MRAM. A significant research effort is also being devoted to developing MTJs with perpendicular magnetic anisotropy (PMA) materials [2] to achieve acceptably low switching currents, e.g., < 25 uA.

Scaling is not without challenges, however, and the STT-MTJ arrays must, e.g., exhibit sufficient statistical margins between reading and writing operations, and must satisfy other key design properties including, a) sufficient TMR for the read signal, and b) a high enough energy barrier for up to 10 years of data retention. It has been found that fabrication processes like MTJ etching play key roles in MTJ performance to realize the full potential of newly-developed PMA materials, e.g., the ability to approach the resistance-area product RA measured by current-in-plane tunneling (CIPT) [3] on unprocessed MRAM stacks.

The semiconductor industry seems to be preparing for large-scale manufacturing of STT-MRAM, by converging on an IBE-centered etching approach, followed by in situencapsulation. Minimizing metallic redeposition on the edge of the tunnel barrier during etching, and of edge-related magnetic damage, are key challenges in STTM patterning using IBE. Ohsawa et al. [4] showed that a typical MRAM IBE etching energy, e.g., 200 eV, causes a damage layer several monolayers thick at the patterned surface, suggesting that lower beam energies would be necessary during etching, or at least in the final damage-removal step. Confirming the promise of IBE, Samsung researchers Song et al. [5] recently reported high yields for an embedded STT-MRAM, patterned using IBE, with 8-Mbit density and a cell size of 0.0364 sq. micron.

At IBM, following conventional 193 nm lithography, we have typically employed a RIE etch to pattern a Ta-based MTJ hardmask, stopping on a protective cap layer, which is then followed by MRAM stack etching using a combination of a MeOH-based RIE and IBE. Using arrays of different lithographically-printed MTJ mask diameters, final etched device sizes ranging from a high of about 100 nm down to 10 nm or less are typically obtained, as confirmed by TEM [6, 7].

Using this patterning approach, we demonstrated good STT performance down to 10-6 write-error-rate (WER) in a wide range of device sizes from 50 nm to 11 nm for a specific PMA STT-MRAM stack, for a statistically relevant sample of more than 650 devices [7]. We further demonstrated an individual 11 nm device switching down to WER = 7*10-10at 10 ns using only 7.5 uA current.

[1] J. C. Slonczewski, J. Magn. Magn. Mater.,159, L1 (1996).

[2] For ex., D. C. Worledge et al., IEDM Tech. Dig., 296 (2010); S. Ikeda et al., Nature Mater., 9, 721 (2010).

[3] D. C. Worledge and P. L. Trouilloud, Appl. Phys. Lett., 83, 84 (2003).

[4] Y. Ohsawa et al., IEEE Trans. Magn., 52, 1 (2016).

[5] Y.J. Song et al., IEDM, paper 27.2, (2016).

[6] M. Gajek et al., Appl. Phys. Lett., 100, 132408 (2012).

[7] J. J. Nowak et al., IEEE Magn. Lett., 7, 1 (2016).


We wish to thank E. Galligan, for technical support. The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where the magnetic device layers were fabricated.