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Temperature Dependence of Defect Evolution and Distribution in Thermally Cycled Cu-TSVs

Tuesday, May 13, 2014: 08:40
Taylor, Ground Level (Hilton Orlando Bonnet Creek)
J. B. Marro (Clemson University, University of Central Florida), C. A. Okoro, Y. S. Obeng (NIST), K. A. Richardson (University of Central Florida, Clemson University), and K. Chamma (University of Central Florida)
Through-silicon vias (TSV) are copper (Cu) interconnects used in three dimensional integrated circuits (3D-IC) and other packaging to allow inter-chip communication.  A thermo-mechanical reliability concern for Cu-TSVs, are the formation of voids, which are indicative of the stresses undergone by the structures.  Voids can degrade signal propagation by acting as scattering centers and if large enough, can prevent the passage of current [1].  Simulations of fabrication conditions such as back-end-of-the-line (BEOL) addition, have been conducted by isothermal heating or minimal cycling [2-4]; however, few studies have focused on in-use conditions where chips undergo many cycles at lower temperatures, simulating environmental changes and joule heating from use.  This study replicates these in-use conditions to evaluate defect evolution and distribution in thermally cycled Cu-TSVs.  Silicon (Si) chips containing blind Cu-TSVs were cycled 2000 times from room temperature to maximum cycling temperatures of 100 °C, 150 °C, or 200 °C.  Residual voiding from fabrication was considered by examining two sample types (shown in Fig. 1), specimens that contained Cu-TSVs with seams and large bottom voids and those that exhibited only microvoids.  The S11 parameter was measured at 500 cycle increments and determined signal loss trended with maximum cycling temperature and initial void area, but not with number of cycles.  To further investigate void development, the TSVs were cross-sectioned for internal evaluation using a combination of grinding, polishing, and ion beam milling.  Voids were then studied using focus ion beam (FIB) and scanning electron microscope (SEM) images to record void dimensions and locations within the Cu of the TSVs.  Void area was observed to increase with increasing maximum cycling temperature from 100 °C to 200 °C, however, this increase is a result of void nucleation as opposed to pre-existing void growth.  While rapid cycling (~5 min/cycle) under in-use conditions for these Cu-TSVs did not allow diffusion and growth of voids, maximum cycling temperatures provided sufficient driving force for stresses to form new voids in the Cu.

Fig. 1: SEM micrographs of the TSV cross-sections for the two as-received sample types: (a) containing seams and large bottom voids and (b) solely containing microvoids.

References:

1. J. Kim, J. Cho, J. S. Pak, J. Kim, J. Yook, and J. C. Kim, Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on 243-246 (2011).

2. H. Shin, B. Kim, J. Kim, S. Hwang, A. Budiman, H. Son, K. Byun, N. Tamura, M. Kunz, D. Kim and Y. Joo, Journal of Electronic Materials, 41 [4] 712-719 (2012).

3. L. W. Kong, J. R. Lloyd, K. B. Yeap, E. Zschech, A. Rudack, M. Liehr and A. Diebold, Journal of Applied Physics, 110 [5] 053502 (2011).

4. L. Kong, A. C. Rudack, P. Krueger, E. Zschech, S. Arkalgud and A. C. Diebold, Microelectronic Engineering, 92 [0] 24-28 (2012).