Copper Damascene

Wednesday, 8 October 2014: 10:20-12:00
Expo Center, 1st Floor, Universal 13 (Moon Palace Resort)
Chairs:
Wei-Ping Dow and F. Roozeboom
10:20
1705
Impurity in the Electroplated Sub-50nm Cu Lines
Q. Huang (IBM, T. J. Watson Research Center), A. Avekians (IBM T. J. Watson Research Center), S. Ahmed (IBM Semiconductor Research & Development Center), C. Parks (IBM Semiconductor Research and Development Center), B. Baker-O'Neal (IBM, T. J. Watson Research Center), S. Kitayaporn (IBM T.J. Watson Research Center), A. Sahin (IBM, T. J. Watson Research Center), Y. Sun (IBM T. J. Watson Research Center), and T. Cheng (IBM Semiconductor Research & Development Center)
10:40
1706
Effect of Flow and Wafer Rotation on the Metallization of Copper Interconnects
L. Boehme and U. Landau (Case Western Reserve University)
11:00
1707
Electroless Deposition of Cu-Mn Alloy
L. Yu and R. Akolkar (Case Western Reserve University)
11:20
1708
Barrier Metal Slurry for Low Defect Copper Damascene Chemical Mechanical Polishing
H. Kim, K. Seo, J. Moon, H. Kim, and H. Hwang (Memory Clean/CMP Technology Team, Samsung Electronics)
11:40
1709
Case Study of Early Detection of Iron Contamination in Copper Damascene Plating Process by In-Situ Electrochemical Sensor
A. Jaworski, H. Wikiel, K. Wikiel (Technic, Inc.), P. Holverson, and A. Nelson (Texas Instruments, Inc.)
See more of: P5: Processing Materials of 3D Interconnects, Damascene, and Electronics Packaging 6
See more of: Electronic Materials and Processing
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