We have worked to detect all the visible defects present in our epitaxial layers. However due to the large variety of defects present and their varying effect on device performance, just detection is not enough. The defects have to be finely classified into various defect types to gauge their electrical impact. We have classified the defects into various types of triangular defects, fall-down particles, carrots, scratches, pits, step bunching, V-type defects [2,3], large and small topographic defects and defects related to manual handling. Through an iterative process involving electrical characterization of fabricated Schottky barrier diodes (SBD) we have determined which of these classes are killer defects. It is found that mainly fall-down particles, a subset of triangular defects, carrots and large topographic defects are the main causes of electrical failure at wafer sort. Other defects like fainter obtuse triangular defects , V-type defects, scratches, step-bunching and pits do not cause outright fails. Second degree effects are observed for many of these non-killer defect types. Other purely crystal defects having no visible defect signatures like basal plane dislocations, stacking faults, grain boundaries were also detected and classified. However these were also determined not to have any influence on SBD device yield at wafer sort.
Once the killer defects are determined after epitaxial growth, we created a yield model based on the actual die grid of our actual physical device layout. The yield prediction of this model was tested experimentally and validated for different wafers across multiple lots. A very close agreement of ±2% was observed across all the wafers. This model enables us to predict wafer yield right after epitaxy and before starting the wafers in the fabrication line very accurately. As product lines involve multiple current ratings with different die sizes, a further enhancement of this model was done to predict the yield on a wide variety of die sizes corresponding to device current ratings ranging from 2 Amps to 20 Amps. The predicted yield was validated experimentally and was found to be accurate within ±0.5%. The accuracy of both these models enables very efficient binning of epitaxial wafers to the correct device die size to ensure optimum yield at electrical wafer sort.
It is also important to gauge the impact of the non-killer defects on the electrical properties of various devices. Our analysis shows that some of these defects cause slightly increased leakage currents both in the forward conduction and reverse blocking conditions without causing the devices to fail. More extensive measurements and reliability testing is needed to understand some of the longer term impacts of the presence of these classes of defects in the SiC material.
Both the above yield models along with the validation against experimental data will be presented. A detailed description of the various classified defect types will be presented. Second order effects of the non-killer defect types on electrical tests will also be discussed.
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