E12 ULSI Process Integration 8

Lead Organizer: Cor Claeys (imec)

Co-organizers: S. Deleonibus (CEA-LETI) , Hiroshi Iwai (Tokyo Institute of Technology) , Junichi Murota (Tohoku University) and M. Tao (University of Texas at Arlington)

Monday, October 28, 2013

08:55-10:30


Keynote Presentations
Continental 7, Tower 3, Ballroom Level
Chair(s): Cor Claeys

10:30-12:00


Back-end Processing 1
Continental 7, Tower 3, Ballroom Level
Chair(s): Eric Eisenbraun and Hiromu Ishii, D. Sc.

14:00-15:00


Single Electron Transistors
Continental 7, Tower 3, Ballroom Level
Chair(s): Michiharu Tabe

15:00-16:30


Technology Trends
Continental 7, Tower 3, Ballroom Level
Chair(s): Oliver Faynot

Tuesday, October 29, 2013

08:10-09:40


3-5 Technologies
Continental 7, Tower 3, Ballroom Level
Chair(s): S. Deleonibus

10:00-12:10


Epitaxial Processing
Continental 7, Tower 3, Ballroom Level
Chair(s): Seiichi Miyazaki and Hiroshi Iwai

14:00-15:40


Ge-based Technologies
Continental 7, Tower 3, Ballroom Level
Chair(s): Hiroshi Iwai and Peide D Ye

16:00-17:30


Front-end Processing
Continental 7, Tower 3, Ballroom Level
Chair(s): Junichi Murota and Vinh Le Thanh

Wednesday, October 30, 2013

08:40-09:40


Back-end Processing 2
Continental 7, Tower 3, Ballroom Level
Chair(s): Makoto Hirayama

10:00-11:30


Tunneling and Quantum Devices
Continental 7, Tower 3, Ballroom Level
Chair(s): Marc Sanquer

14:00-15:50


Device Characterization
Continental 7, Tower 3, Ballroom Level
Chair(s): Toshiaki Tsuchiya and Junichi Murota